1. Field of the Invention
This invention relates to a method of manufacturing an active matrix display device, and more particularly to a method of forming insulation layers used in the active matrix display device. In the active matrix display device, a plurality of display elements are arranged in rows and columns and driven by a plurality of thin film transistors located at each display element position. The insulation layers are used for forming thin film transistors, in which a gate insulation layer and a protection layer covering the thin film transistor are formed. Further, two groups of bus lines are formed on a substrate in the row and column directions respectively to drive the thin film transistors, and two groups are to be insulated from each other at the crossing points by an inter-busline insulation layer. In some cases, the active matrix display device provides an auxiliary capacitor for each display element, the capacitor having a capacitor insulation layer. The present invention relates to the method of forming any of the above insulation layers.
2. Description of the Related Art
Thin film transistors (hereinafter abbreviated as TFT) are used in an active matrix display device to drive each display element. The TFT has a gate insulation layer formed between a gates electrode and an amorphous silicon semiconductor layer. In Order to drive each TFT, gate bus lines and drain bus lines are formed in the row and column directions respectively. The gate bus line and drain bus line must be insulated from each other by insulation layer at the crossing point. Further, it is necessary to cover and to protect at least TFT region with an protection layer at the final stage of fabrication of a substrate.
Thus insulation layers are needed at different portions of the display device structure and are formed at different phases in fabrication. In active matrix display devices having TFTs, materials such as indium tin oxide (abbreviated as ITO), amorphous silicon and aluminum are utilized. These materials require process temperatures as low as possible during=the processes. Therefore, insulation layers are preferably deposited at low substrate temperatures which will not cause bad effects on the grown material. A plasma CVD method is known as a low temperature CVD process and is widely used in manufacturing active matrix display devices.
In forming the TFT, for example, a metal layer is first deposited on a substrate and is patterned, with a result of forming a gate electrode. A gate insulation layer is next formed thereon. The gate insulation layer is of silicon nitride (SiN.sub.x) or silicon oxynitride (SiON), and is formed on the substrate by the plasma CVD method, in which the substrate temperature is maintained at around 350.degree. C. Thereafter, an amorphous silicon (a-Si:H) is deposited on the surface of the gate insulation layer using the same plasma CVD apparatus without a break of vacuum, only source gases being changed. After patterning the amorphous silicon layer, source and drain electrodes are formed thereon, thus the TFTs are formed on the substrate.
In the similar way, an inter-busline insulation layer, which insulates gate bus lines from drain (or source) bus lines, is formed by the plasma CVD method. Sometimes, the inter-busline insulation layer is formed simultaneously with the forming step of gate insulation layer using the same plasma CVD apparatus.
The substrate (first substrate) is sealed with another opposite (second) substrate at the final stage of display device fabrication, and light influencing material such as liquid crystal is sealed between two substrates. Therefore, another insulation layer is necessary in order to protect amorphous silicon (a-Si:H) portions on the first substrate before the sealing process. The protection (insulation) layer is deposited at least on the TFT portions in the similar way.
In order to improve picture quality of active matrix display devices, it is known that an auxiliary capacitor is formed in the display device arranged at each corresponding position to the display elements. In this case, a transparent electrode of the display element connected to the source electrode of the TFT is utilized as a first electrode of the auxiliary capacitor, and either an extended portion of the adjacent gate bus line or a separately formed earth busline is utilized as a second capacitor electrode, thereby a capacitor insulation layer being formed between these two electrodes of the auxiliary capacitor.
Existing four kinds of insulation layers such as gate insulation layer, inter-busline insulation layer, protection layer and capacitor insulation layer, which are generally formed by the known plasma CVD method at low temperatures, have essentially a drawback of poor covering capability when deposited on the substrate surface having steps. The formed insulation layer is weak in mechanical strength and easily forms cracks, resulting in decreasing a withstanding voltage and insulation resistance of the insulation layer.
Replacing the existing plasma CVD method, other CVD methods having a different idea of deposition are disclosed in the following patents:
U.S. Pat. No. 4,058,430 issued on Nov. 15, 1977 to Tuomo Suntola etal. entitled "Method for producing compound thin films";
U.S. Pat. No. 4,486,487 issued on Dec. 4, 1984 to Jarmo I. Skarp entitled "Combination film, in particular for thin film electroluminescent structures"; and
U.S. Pat. No. 4,389,973 issued on Jan. 28, 1983 to Tuomo S. Suntola etal. entitled "Apparatus for performing growth of compound thin films".
The principle of the above disclosures is to utilize in common the so-called "atomic layer epitaxy" method which is abbreviated as "ALE" method.
The method of U.S. Pat. No. 4,058,430 comprises the steps of subjecting the substrate to the vapor of a first kind of element forming a single atomic layer, and subjecting thus formed surface of the single atomic layer to the vapor of a second kind of element which can react with the first element resulting in forming a single layer of compound of first and second elements. These steps are repeated until a desired thickness can be obtained. The method discloses formation of thin films of light emitting semiconductor or resistance layers.
U.S. Pat. No. 4,486,487 discloses a method of forming a combination film of aluminum oxide and titanium oxide utilizing the ALE method.
U.S. Pat. No. 4,389,973 discloses a method and an apparatus for forming a compound thin films such as tantalum oxide, zinc sulphide and aluminum oxide by the ALE method emphasizing the apparatus used therefor.